Challenges Extending Copper Interconnects at 5nm Exponential resistance increase Gapfill limitations of ECD >20nm Top Opening (a.u.) 1 sistance 2 PVD Cu seed ECD bottom-up Cu fill re <20nm Top Opening 3 ia V 10nm 7nm 5nm 3nm Node PVD Cu seed ECD bottom-up Cu fill 1 Limited space for metal wire 3 Trapped voids 2 High-resistance interfaces a.u.: arbitrary units