Limitations of Frontside Power Distribution Network Architecture Power Delivery Losses (voltage drop)  Power delivery network CMOS top metal ign margin permits des 10% IR drop p  Large IR drop from o r 12+ metal levels due Voltage source CMOS die e d g a t to resistance Power ol V regulator Package substrate  Excessive IR drop Printed circuit board (~50%) creates reliability issues Source: Adapted from 2019 Lithography Workshop CMOS transistor