GAA with Backside Power Network for Additional Area Scaling 6 4 2 0 20 to 30% cell area reduction -2 Performance with Backside Power Network Area -4 Power ↓5.5x 7.5x ↓ -6 16/12nm 2nm GAA w/ -8 Planar (FinFET) 7nm 3nm (GAA) BPN -1 0 Intrinsic Intrinsic scaling scaling + 40% DTCO + >50% DTCO 20-30% area scaling from DTCO th Planar 5 Gen FinFET GAA or Variants GAA with (5nm) (2nm) Backside Power Network BPN: Backside Power Network