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New Ways to Wire and Integrate Chips MASTER CLASS May 26, 2022 Applied Materials External 1

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2022 MASTER CLASSES WELCOME Michael Sullivan Corporate Vice President Head of Investor Relations NEW WAYS TO WIRE AND INTEGRATE CHIPS MASTER CLASS | MAY 26, 2022

2022 Master Classes APRIL MAY 21 26 New Ways New Ways to to Shrink Wire and Integrate Chips

9:00 PART 1 Mike Sullivan NDA Introduction and Fireside Chat with Regina Freed E Kevin Moraes, Ph.D. G Solving the Resistance Challenges of EUV Scaling A Mehul Naik, Ph.D. 9:05 PART 2 Enabling Backside Power Distribution Networks Sundar Ramamurthy, Ph.D. Enabling Heterogenous Chip Integration with Hybrid Bonding and Advance Substrates 9:45 PART 3 Raman Achutharaman, Ph.D. Growth in Chip Wiring and Integration 9:50 PART 4 Q&A Mehul, Sundar, Raman, Mike

2022 Master Classes APRIL MAY Sept 21 26 22* New Ways New Ways to Subscriptions to Shrink Wire and and Integrate Services Chips * Target date

T CHA IDE S Regina Freed Vice President FIRE Semiconductor Products Group

Solving the Resistance Challenges of EUV Scaling Kevin Moraes, Ph.D. Vice President Semiconductor Products Group NEW WAYS TO WIRE AND INTEGRATE CHIPS MASTER CLASS | May 26, 2022 8 Applied Materials External

Creating Amazing Digital Experiences with Billions of Transistors Chip-to-Chip On-Chip Interconnects Interconnects Brought to you by: 1. Low-resistance wiring 2. Backside power distribution networks 3. Heterogenous integration

Wiring Transistors On a Chip Interconnects  Make connections laterally vertically and Lines + Vias  Over 15 metal layers  4-5 layers at minimum pitch  Smallest widths ~14nm Contacts  Connect transistors to Via contacts interconnects Trench contacts  One or two metal layers Gate  Smallest widths ~12nm Fin Image source: TechInsights and Applied Materials

Creating Transistor Contacts Via contacts Top View  Connect contact to Fabrication requires: interconnect  Bottleneck for current flow  Barrier layer to protect transistor Trench contacts Side View  Seed layer to  Connect contact to transistor facilitate fill  Must not contaminate channel  Metal fill to conduct current Contacts made of Barrier and seed layers reduce space tungsten or cobalt available for metal contact wire

Creating Interconnects Between Transistors Interconnects Fabrication requires:  Lines make lateral  Barrier to block connections within each Line copper diffusion layer; vias connect layers Via  Liner to improve Barrier copper adhesion Chips have >50 miles of on Cu  Seed layer for Line copper growth copper interconnect wiring  Copper fill to com plete wire Resistance impacts power Barrier layers increase via resistance, cause and performance RC delays, waste power

Resistance Increases Exponentially as Wiring Scales Contact resistance Via resistance .) u a. ) ( . e u c a. an ( t e s c i >4x an >10x es t r s t i ac es t a r on i C V 10nm 7nm 5nm 3nm 10nm 7nm 5nm 3nm Node Node Assumptions: Dimensions scale; liner/barrier materials and dimensions do not a.u.: arbitrary units

Contact Resistance Innovations Endura® iLB PVD/ALD Endura Volta® W CVD Endura Volta Co CVD Endura Volta Selective W CVD 2010 2016 2018 2020 Radical-enhanced Tungsten carbide Cobalt fill Liner-free selective ALD TiNbarrier barrier and liner product suite tungsten fill

™ EnduraIoniq W PVD: Low-Resistance Tungsten Contacts Integrated Materials Solution™for pure tungsten metal gapfill neering, PVD  Combines interface engi and CVDin high-vacuum  Enablescontactscaling in a wide variety of applications

™ EnduraContact Metal IMS System Pure W fill Pure W liner Metal surface treatment Integrated Materials Solution Enables Pure Metal Contacts

Contact Resistance Innovations Continue Endura iLB PVD/ALD Endura Volta® W CVD Endura Volta Co CVD Endura Volta Endura Ioniq Selective W CVD W IMS 2010 2016 2018 2020 2022 Radical-enhanced Tungsten carbide Cobalt fill Liner-free selective PVD W liner ALD TiNbarrier barrier and liner product suite tungsten fill and CVD W fill

Innovations to Extend Copper Interconnects 2012 Endura CuBS RF XT PVD High-coverage 2014 barrier & seed Endura Volta Cobalt CVD Seed enhancing cobalt liner & selective metal cap 2018 Endura CuBS ALD/PVD 2021 ALD barrier Endura Copper Barrier Seed IMS Selective barrier & copper reflow

Copper Interconnect Fabrication Endura Copper Barrier System ECD System Integrated Materials Solution Non-integrated H* H* H*    + Surface treatment PVD tantalum CVD cobalt PVD copper ECD copper fill removes residue nitride barrier liner seed

Challenges Extending Copper Interconnects at 5nm Exponential resistance increase Gapfill limitations of ECD >20nm Top Opening (a.u.) 1 sistance 2 PVD Cu seed ECD bottom-up Cu fill re <20nm Top Opening 3 ia V 10nm 7nm 5nm 3nm Node PVD Cu seed ECD bottom-up Cu fill 1 Limited space for metal wire 3 Trapped voids 2 High-resistance interfaces a.u.: arbitrary units

Lowering Via Resistance with Selective ALD Barriers Standard barrier integration Via resistance reduction Barrier .) .u Standard Barrier a e ( +100% -47% c an t s i +5% es Selective ALD barrier integration r Selective ALD barrier a i V Thin 5nm 3nm No Node dep Selective ALD removes high-resistance interface Surface Selective Treatment engineering ALD barrier

Reliable Copper Gapfillwith PVD Copper Reflow Copper reflow sequence Repeat cycles First deposition Warm reflow Wafer cool Next deposition Complete fill with PVD copper reflow Image source: Applied Materials

Unique IMS Solutions Address Resistance Issues of EUV Scaling Contact scaling with new materials / schemes .) (a.u New IMS nce solution resista Faster transistors tact Con10nm 7nm 5nm 3nm 7nm 3nm Node Interconnect scaling with new materials / schemes (a.u.) New IMS solution sistance Improved power re ia V 10nm 7nm 5nm 3nm 7nm 3nm Node

Enabling Backside Power Distribution Networks Mehul Naik, Ph.D. Managing Director and Principal Member of Technical Staff Semiconductor Products Group NEW WAYS TO WIRE AND INTEGRATE CHIPS MASTER CLASS | May 26, 2022 Applied Materials External 24

Device Scaling Approaches Contribution to Logic Density Scaling Intrinsic Scaling DTCO Intrinsic Scaling DTCO N N N+1 N+1 >50% >40% 1% >25% 16nm 10nm 7nm 5nm 3nm Source: M. Liu/TSMC, ISSCC 2021 DTCO: Design Technology Co-Optimization DTCO is becoming an increasingly important contributor to scaling

Future of Logic Scaling PPA Improvements Scaling Benefits 6 4 ↑3.5x 2 0 Performance 3.5x ↑ -2 Performance ? Area -4 Power ↓5.5x -6 ↓6.0x Power 6.0x ↓ 16/12nm 2nm -8 Planar (FinFET) 7nm 3nm (GAA) -1 0 Area 5.5x ↓ Intrinsic Intrinsic scaling scaling + 40% DTCO + >50% DTCO ? 5th Gen FinFET GAA or Variants Next Gen Planar (5nm) (2nm) Area Scaling

Limitations of Frontside Power Distribution Network Architecture Power Delivery Losses (voltage drop)  Power delivery network CMOS top metal ign margin permits des 10% IR drop p  Large IR drop from o r 12+ metal levels due Voltage source CMOS die e d g a t to resistance Power ol V regulator Package substrate  Excessive IR drop Printed circuit board (~50%) creates reliability issues Source: Adapted from 2019 Lithography Workshop CMOS transistor

Limitations of Frontside Power Distribution Network Architecture Cell Area Scaling Challenge Gate Power rail Gate Signal line Signal line Fin Frontside power rail Removing frontside CD ~3x min CD power rail enables cell area scaling

PPACtBenefit of Backside Power Distribution Network Inflection Frontside Scheme Backside Scheme Power delivery Power and Signal lines Reduced Maintain 10% signal lines only Voltage design margin Power rail Drop Power rail Transistor Power line Area 20 to 30% Savings cell area Power delivery reduction Key changes  Separation of power and signal lines  Power delivery from backside of the wafer Source: Adapted from multiple IMEC and ARM publications

GAA with Backside Power Network for Additional Area Scaling 6 4 2 0 20 to 30% cell area reduction -2 Performance with Backside Power Network Area -4 Power ↓5.5x 7.5x ↓ -6 16/12nm 2nm GAA w/ -8 Planar (FinFET) 7nm 3nm (GAA) BPN -1 0 Intrinsic Intrinsic scaling scaling + 40% DTCO + >50% DTCO 20-30% area scaling from DTCO th Planar 5 Gen FinFET GAA or Variants GAA with (5nm) (2nm) Backside Power Network BPN: Backside Power Network

Backside Power Distribution Network Architecture Signal line  Multiple approaches in Transistor development Power transferred to transistor using multiple approaches fs between Copper power line  Trade-of power/area scaling and manufacturing complexity Power delivery from external power supply Source: Adapted from multiple IMECpublications Applied Materials External

Announced Backside Power Distribution Network Approaches Buried Power Rail Power Via Backside Contact to S/D Power Backside Buried n-TSV via power rail contact Power delivery Area Scaling Good Better Best Process Complexity Low Medium High Source: Adapted from Song et al (IEDM, 2021) Source: Adapted from public company disclosures (2021) Source: Adapted from Song et al (IEDM, 2021) with subsequent analysis by Applied Materials with subsequent analysis by Applied Materials with subsequent analysis by Applied Materials

Frontside and Backside Wafer Fabrication

Broad Portfolio Addresses all Backside Power Distribution Schemes = Broadest Portfolio of Unit Processes Co-Optimized Solutions Integrated Materials Solutions Next-Generation Scaling ™ Unit Process Leadership* Co-Optimization for IMS Metal Co-Optimized with CMP ® ® Low-Temperature Dopant Activation ReflexionLK Prime Silicon and Dielectric CMP ® ® Centura Prime Epi Endura®IMS Metal ® ® ™ Producer Eterna FCVD  Silicide Backside Isolation Fill  Contact Liner Fill  Copper Barrier Seed VIISTA® 900 3D Implant IMS ® ® Centris SYM3 Y n-TSV Etch ReflexionLK Prime ® ® ™ New Metal CMP Olympia ALD Astra DSA Anneal n-TSV Isolation * Partial List

Frontside and Backside Wafer Fabrication Utilizing the backside of wafer for power delivery

New Ways to Integrate Chips Sundar Ramamurthy Group Vice President, GM Semiconductor Products Groups NEW WAYS TO WIRE AND PACKAGE CHIPS MASTER CLASS | May 26, 2022

Heterogeneous Chip Design –An Evolution of Moore’s Law Heterogenous integration “It may prove to be more economical to build e large systems out of smaller functions, which nu are separately packaged and interconnected.” e - Gordon Moore, 1965 v e R y r t s Flip-chip du n ERA 4: AI I r o Wire bonding t c du on c i em S ERA 3: Mobility ERA 2: PC + Internet ERA 1: Mainframe Source: SEMI, VLSI, Applied Materials https://archive.computerhistory.org/resources/access/text/2017/03/102770822-05-01-acc.pdf PC: Personal Computer AI: Artificial Intelligence

Traditional Moore's Law Scaling Hits Limits Microprocessor Trends 108 Transistor (k) 107 Single thread performance (SpecINTx 1000) 106 Frequency (MHz) Typical power (Watts) 105 Number of cores 104 103 102 101 100 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020  Single-threaded processor performance has plateaued despite increases in cores and transistors  Application accelerator performance continues to scale with cores and transistors Source: https://www.karlrupp.net/wp-content/uploads/2018/02/42-years-processor-trend.png Source: https://www.karlrupp.net/wp-content/uploads/2018/02/42-years-processor-trend.png MHz: Megahertz Source: Yole Développement Source: https://www.techspot.com/article/2143-ryzen-5000-ipc-performance/ SpecINT: computer benchmark specification for CPU integer processing power

Transistor Counts are Hitting the Reticle Limit 1700 1500 Reticle limit 1300 2)1100 m AMD m Reticle limit (900 e iz s700 Nvidia Die 500 300 Intel Apple 100 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022E 2023E Source: Jefferies

Opportunity: Heterogeneous SRAM Integration g n i al c ea S r A SRAM SRAM cache memory is key to performance Limited 2D scaling of SRAM impacts die size and yield Logic 28nm 16nm 10nm 7nm 5nm 3nm 2nm Source: Naffziger, VLSI Short Course, 2020 SRAM: Static Random Access Memory Source : Yole Développement

Heterogenous Integration to the Rescue GPU Memory CPU RF Image Sensor Heterogeneous integration enables logic, memory, sensors, power and communications to be combined as a system-in-package RF: Radio Frequency GPU: Graphics Processing Unit CPU: Central Processing Unit

Advanced Interconnects Enable “System-in-Package” Era Hybrid bonding Advanced substrates HBM GPU Hybrid bonding enables up to Advanced substrates connect multiple >10,000I/Os per mm2 high-performance die at high I/O density and data bandwidth HBM: High bandwidth memory I/O: Input / Output

Hybrid Bonding for High-Density Chip-to-Chip Interconnects Hybrid bonding Approaches Wafer-to-wafer Die-to-wafer Dielectric materials and copper pads fuse 2  Enables >10,000 connections per mm  Requires precision in processing and alignment  SoC performance can be reconstituted and Multiple hybrid bonding options expanded with hybrid bonded chiplets SoC: System on a chip

End-to-End Portfolio of Hybrid Bonding Solutions Producer® CVD Producer® Etch Endura® Mustang® Reflexion® LK ™ Integrated Materials Solution for hybrid bonding Substrate Dielectric stack Damascene RDL / Barrier / seed PVD Copper pad fill CMP with tuned Surface Hybrid bond Anneal and finish CVD pad formation etch ECD dishing control preparation (D2W or W2W) bonding  Collaborating with partners to develop end-to-end technologies to ramp hybrid bonding solutions  Center of Excellence investigates materials and process interactions on custom test vehicles CVD: Chemical Vapor Deposition ECD: Electrochemical deposition RDL: Redistribution layer CMP: Chemical mechanical polishing PVD: Physical vapor deposition D2W: Die to wafer W2W: Wafer to wafer

Integrated Materials Solution for Chip-to-Wafer Hybrid Bonding Film Frame Wafer Clean Wafer Clean UV: Ultraviolet

Advanced Substrates Improve I/O Density and Power 10,000 Advanced flip-chip substrates 1,000 Flip-chip substrates 2 2 m >1,000 I/O/mm m <0.1 pJ/bit r 100 e Wire bond substrates 2 I/O p 100-500 I/O/mm >1 pJ/bit 10 2 1-10 I/O/mm >10 pJ/bit 1 1000 100 10 1 Line/space pitch (µm)

System Integration with Emerging 2D and 3D Interconnects Through-Silicon Vias (TSV) Hybrid bonding Chip 1 Source: TechInsights (Chipworks) IMX260 Chip 2 Camera Module Report, 2016 Micro-bump Polymer RDL Flip-chip bump Advanced substrate Polymer RDL/ Si interposer Image Sources: SystemPlus Consulting Reports  Advanced substrates package chips side-by-side with higher bandwidth (more I/Os) and lower power  TSVs with micro-bumps or hybrid bonding create vertical interconnects allowing chip-on-chip stacking

Quest for Performance is Making Packages Larger Package processing must go bigger…  Multiple chipletsin a package  Package areas as large as 10,000mm2  Round wafers have poor area efficiency Panels enable greater number of larger packages Silicon wafer Panel

Semiconductor-Grade Large Substrate Processing ™ Applied Topaz PVD System  Substrates up to 600x600mm  Cluster chamber architecture  Multiple applications supported Creating an industry ecosystem for semiconductor-grade panel-level packaging

Panel-Level eBeam Metrology and Test Defect review with SEM and FIB analysis Non-destructive eBeamtest Protrusion Residuals Normal interconnect Shorts highlighted  Automatic defect review  Fault detection by voltage contrast  Precise CD measurement  High-throughput analysis  In-situ failure analysis  Damage-free eBeam: Electron beam SEM: Scanning electron microscope FIB: Focused ion beam

Wiring & Heterogenous Integration Enable PPACt™ Scaling Low-resistance contacts and 40-50% resistance interconnects reduction @ 3nm • Lower power loss ™ • Faster switching with IMS Backside power distribution networks Up to 30% logic density • Increased logic scaling improvement • Lower power loss vs. frontside power Hybrid bonding and advanced Enables >10,000 I/Os substrates 2 per mm • Heterogenous integration and packages as large • Higher I/O and bandwidth 2 as 10,000mm • Lower power loss IMS: Integrated Materials Solution

Growth in Chip Wiring and Integration Raman Achutharaman, Ph.D. Group Vice President Semiconductor Products Group NEW WAYS TO WIRE AND INTEGRATE CHIPS MASTER CLASS | May 26, 2022 Applied Materials External 52

Semi Systems Revenue Growth Drivers Core PPACtEnablement >100% >50% $6.5B $4.8B $6.5B FY’20 FY’24* FY’20 FY’24* *Represents 2024 Financial Model High Scenario

The New Playbook ENABLED BY KEY INFLECTIONS  New ASICs and accelerators New architectures  New memory / in-memory compute  Specialty, CIS, power  GAA transistors New structures / 3D  Backside power distribution  3D NAND, 3D DRAM  Gate New materials  Contact  Interconnect  EUV enablement New ways to shrink  Materials-enabled patterning  3D patterning control  High-bandwidth memory Advanced packaging  2.5D silicon interposer  3D TSV, hybrid bonding

Inflections Over Time LONGER TERM  3D DRAM EMERGING  Forksheet  CFET  Gate-All-Around  Backside Power EXISTING  Hybrid Bonding  EUV Enablement  eBeam Metrology  Wiring  DRAM HKMG * Partial list of key inflections

Wiring Growth Opportunity Expect to grow wiring revenue at ~3X the rate of WFE 20202024 Contact Interconnect eps t S ~3X >1.5X 7nm 5nm 3nm 7nm 5nm 3nm Applied’s wiring opportunity increases by >$1B from 7nm3nm *Leading Foundry/Logic Customers

Positioned for Growth in Packaging Early innings of multi-year growth  #1 in bond pad, bump and TSV  Broad product portfolio + full-flow lab ~$500M  Key ecosystem partnerships  Delivering system level PPACt gains: ↓ R, ↓ power, ↓ area, FY’20 FY’24F ↑ performance

Packaging Growth Opportunity Revenue Growth Revenue Goal >50% YoY >10% CAGR FY’15 FY’20 FY’21 FY’20 FY’23 FY’24

Packaging Portfolio PVD Plating CMP CVD Etch Future  Integrated Materials Solution for hybrid bonding  Large-area metrology and Endura® Mustang® Reflexion® LK Producer® CVD Producer® Etch process control

Broad Portfolio Addresses all Backside Power Distribution Schemes = Broadest Portfolio of Unit Processes Cooptimized Solutions Integrated Materials Solutions Next-Generation Scaling Buried Power Rail Power Via Backside Contact to S/D Backside Power Delivery Approaches Logic Density, Low Medium High Process Complexity

Inflections Over Time LONGER TERM  3D DRAM EMERGING  Forksheet  CFET  Gate-All-Around  Backside Power EXISTING  Hybrid Bonding  EUV Enablement  eBeam Metrology  Wiring  DRAM HKMG * Partial list of key inflections